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ds96wrl0800 p r e l i m i n a r y 1 1 p reliminary c ustomer p rocurement s pecification Z87001/z87l01 1 rom less s pread s pectrum c ordless p hone c ontroller features n transceiver/controller chip optimized for implement- ation of 900 mhz spread spectrum cordless telephone adaptive frequency hopping transmit power control error control signaling handset power management support of 32 kbps adpcm speech coding for high voice quality n dsp core acts as phone controller zilog-provided embedded transceiver software to control transceiver operation and base station- handset communications protocol user-modi?ble software governs telephone features n transceiver circuitry provides primary cordless phone communications functions digital downconversion with automatic frequency control (afc) loop fsk demodulator fsk modulator symbol synchronizer time division duplex (tdd) transmit and receive buffers n on-chip a/d and d/a to support 10.7 mhz if interface n up to 64 kw of external program memory accessible by the dsp core n bus interface to z87010 adpcm processor n static cmos for low power consumption n 3.0v to 3.6v, -20 c to +70 c, z87l01 4.5v to 5.5v, -20 c to +70 c, Z87001 n 16.384 mhz base clock general description the Z87001 /z87l01 fhss cordless telephone trans- ceiver/controller is expressly designed to implement a 900 mhz frequency hopping spread spectrum cordless tele- phone compliant with us fcc regulations for unlicensed operation. the Z87001 and z87l01 are distinct 5v and 3.3v versions, respectively, of the core device. for the sake of brevity, all subsequent references to the Z87001 in this document also apply to the z87l01 unless specifically noted. the Z87001 is the romless version of the z87000 spread spectrum controller ic. specifically intended to facilitate user specific software development, the Z87001 can ac- cess up to 64 kwords of external program rom. the Z87001 supports a specific cordless phone system design that uses frequency hopping and digital modulation to provide extended range, high voice quality, and low sys- tem costs. the Z87001 uses a zilog 16-bit fixed-point two? comple- ment static cmos digital signal processor core as the phone and rf section controller. the Z87001? dsp core processor further supports control of the rf section? fre- quency synthesizer for frequency hopping and the genera- tion of the control messages needed to coordinate incorpo- ration of the phone? handset and base station. additional on-chip transceiver circuitry supports frequency shift key- ing modulation/demodulation and multiplexing/demulti- device rom * (kwords) ram (words) i/o lines package information Z87001 64 512 32 144-pin qfp z87l01 64 512 32 144-pin qfp note: *maximum accessible external rom
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 2 p r e l i m i n a r y ds96wrl0800 general description (continued) plexing of the 32 kbps voice data and 4 kbps command data between handset and base station. the Z87001 pro- vides thirty-two i/o pins, including four wake-up inputs and two cpu interrupt inputs. these programmable i/o pins al- low a variety of user-determined phone features and board layout configurations. additionally, the pins may be used so that phone features and interfaces are supported by an optional microcontroller rather than by the Z87001? dsp core. in combination with an rf section designed according to the system specifications, zilog? z87010/z87l10 adpcm processor, a standard 8-bit pcm telephone codec and minimal additional phone circuity, the Z87001 and its em- bedded software provide a total system solution. figure 1. system block diagram of a Z87001/z87010 based phone z87010 adpcm processor Z87001 spread spectrum controller rf section z87010 adpcm processor Z87001 spread spectrum controller rf section telephone line interface base station handset codec codec
Z87001/z87l01 zilog romless spread spectrum cordless phone controller ds96wrl0800 p r e l i m i n a r y 3 1 figure 2. Z87001 functional block diagram digital dsp core 256 word ram 0 256 word ram 1 port 0 port 1 adc (1-bit) adc (8-bit) dac (4-bit) dac (4-bit) fsk demodulator fsk modulator (downconverter, limiter discriminator, afc, bit sync, frame sync, snr detector) frame counter(s), event trigger, t/r switch ctrl, power on/off ctrl, analog power receive rate buffer transmit rate buffer z87010 interface antenna select rx vref tx rxsw txsw pao n rfeon syle rssi pwlv ant0 ant1 hbsw resetb test avdd agnd vdd gnd p1[15..0] p0[15..0] vxdata[7..0] vxadd[2..0] vxstrb vxrwb vxrdyb clkout codclk power data[15..0] addr[15..0]
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 4 p r e l i m i n a r y ds96wrl0800 pin description figure 3. 144 pin qfp pin con?uration p04 p05 vdd p06 p07 p08 p09 gnd p010 p011 p012 p013 vdd p014 p015 p10 p11 p12 p13 p14 idata1 idata0 data15 idata4 idata3 idata2 idata7 idata6 idata5 idata10 idata9 idata8 avdd rssi pwlv agnd txsw rxsw syle vdd mclk resetb gnd codclk vxadd0 vxadd1 vxadd2 vdd vxrwb vxstrb vxrdyb gnd pao n agnd tx rx avdd vref rfeon p115 gnd p114 p113 vdd p111 p110 p19 gnd p18 p17 p16 vdd p15 vxdata0 vxdata1 vxdata2 vdd vxdata3 vxdata4 vxdata5 vxdata6 vxdata7 clkout hbsw gnd test vdd ant0 ant1 p00 p01 gnd p02 p03 data0 data1 data2 data3 data4 data5 data6 data7 data8 data9 data10 data11 data12 data13 data14 addr0 idata15 idata14 addr2 addr1 addr8 addr7 addr12 addr11 addr10 p112 gnd addr9 addr3 addr5 addr4 addr6 addr13 addr14 addr15 triadd halt irwb iaddr0 trice intenb eib dspclk idata13 idata12 idata11 iaddr1 iaddr2 iaddr3 iaddr4 1 37 73 109 Z87001
Z87001/z87l01 zilog romless spread spectrum cordless phone controller ds96wrl0800 p r e l i m i n a r y 5 1 table 1. 144 pin qfp pin con?uration no symbol function direction 1 tx analog transmit if signal output 2,141 agnd analog ground 3 rx analog receive if signal input 4,144 av dd analog power supply 5 vref analog reference voltage for rx signal 6 rfeon rf on/off control output 7,9,11,13,15,17,19, 21,23,25,27,29,31, 136,138,140 addr[15..0] dsp core program address bus output 8,12,14,16,20,22,24, 28,30,32,36,37,39, 41,44,46 p1[15..0] general-purpose i/o port 1 input/output 10,26,43,60,77,88, 109,128 gnd digital ground 18,34,51,68,86,102, 116,131 v dd digital power supply 33,35,38,40,42,45, 47,49,52,54,56,59, 61,63,66,69 idata[15..0] dsp core internal data bus output 48,50,53,55,57,58, 62,64,65,67,70,72, 73,75,79,80 p0[15..0] general-purpose i/o port 0 input/output 71,74,76,78,81,83, 85,89,91,93,96,98, 100,103,105,107 data[15..0] dsp core program data bus input 82,84 ant[1..0] rf antenna diversity control output 87 test test mode select input 90 hbsw handset/base mode select input 92 clkout clock, adpcm processor (16.384 mhz) output 94,95,97,99,101, 104,106,108 vxdata[7..0] adpcm processor data bus input 110 vxrdyb adpcm processor ready output 111 eib external register data strobe output 112 vxstrb adpcm processor data strobe input 113,117,119,121, 123 iaddr[4..0] external register address bus output 114 vxrwb adpcm processor read/write control input 115 trice romless mode select input 118,120,122 vxadd[2..0] adpcm processor address bus input 124 codclk clock to codec (2.048 mhz) output 125 irwb external register read/write control output 126 /resetb master reset input 127 intenb interrupt enable input
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 6 p r e l i m i n a r y ds96wrl0800 pin description (continued) 129 halt halt/ single step control input 130 mclk master clock (16.384 mhz) input 132 triadd program address bus enable input 133 paon rf transmit enable output 134 dspclk dsp core clock output 135 syle rf synthesizer load enable output 137 rxsw demodulator ?n indication output 139 txsw rf receive enable output 142 pwlv rf transmit power level input 143 rssi rf receive signal strength indicator input table 1. 144 pin qfp pin con?uration no symbol function direction
Z87001/z87l01 zilog romless spread spectrum cordless phone controller ds96wrl0800 p r e l i m i n a r y 7 1 absolute maximum ratings stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is a stress rating only; operation of the device at any condition above those indicated in the operational sec- tions of these specifications is not implied. exposure to ab- solute maximum rating conditions for extended period may affect device reliability. standard test conditions the electrical characteristics listed below apply for the fol- lowing standard test conditions, unless otherwise noted. all voltages are referenced to gnd. positive current flows into the referenced pins. standard test conditions are as follows: n 3.0v < v dd < 3.6v (z87l01) n 4.5v < v dd < 5.5v (Z87001) n gnd = 0v n t a = -20 to +70 c symbol parameter min max units v dd , av dd dc supply voltage(1) -0.5 7.0 v v in input voltage(2) -0.5 v dd + 0.5 v v out output voltage(3) -0.5 v dd + 0.5 v t a operating temperature -20 +70 c t stg storage temperature -65 +150 c notes: 1. voltage on all pins with respect to gnd. 2. voltage on all inputs wrt vdd 3. voltage on all outputs wrt vdd figure 5. test load diagram output under test iol ioh threshold voltage 50pf
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 8 p r e l i m i n a r y ds96wrl0800 recommended operating conditions table 3. 5v 0.5v operation (Z87001) symbol parameter min max units v dd , av dd supply voltage 4.5 5.5 v v ih input high voltage 2.0 v dd + 0.3 v v il input low voltage gnd -0.3 0.8 v i oh output high current -2.0 ma i ohice output high current, ice pins (1) -0.5 ma i ol1 output low current 4.0 ma i ol2 output low current, gpio (limited usage, 2) 12.0 ma i olice output low current, ice pins (1) 0.5 ma t a operating temperature -20 +70 c notes: 1. ice pins are addr[15..0], iaddr[15..0], idata[15..0], eib and irwb 2. maximum 3 pins total from p0[15..0] and p1[15..0] table 4. 3.3v 0.3v operation (z87l01) symbol parameter min max units v dd supply voltage 3.0 3.6 v v ih input high voltage 0.7 v dd v dd +0.3 v v il input low voltage gnd -0.3 0.1 v dd v i oh output high current -1.0 ma i ohice output high current, ice pins (1) -0.5 ma i ol1 output low current 2.0 ma i ol2 output low current, ports (limited usage, 2) 6.0 ma i olice output low current, ice pins (1)) 0.5 ma t a operating temperature -20 +70 c notes: 1. ice pins are addr[15..0], iaddr[15..0], idata[15..0], eib and irwb 2. maximum 3 pins total from p0[15..0] and p1[15..0]
Z87001/z87l01 zilog romless spread spectrum cordless phone controller ds96wrl0800 p r e l i m i n a r y 9 1 dc electrical characteristics conditions for dc characteristics are corresponding oper- ating conditions, and standard test conditions, unless oth- erwise specified. table 5. 5v 0.5v operation (Z87001) symbol parameter test condition min max units v oh output high voltage v dd min, i oh max 2.4 v v ohice output high voltage, ice pins (1) v dd min, i ohice max 2.4 v v ol1 output low voltage v dd min, i ol1 max 0.6 v v ol2 output low voltage, gpio (2) v dd min, i ol2 max 1.2 v v olice output low voltage, ice pins (1) v dd min, i olice max 0.4 v i l input leakage v in = 0v, v dd -2 2 m a i cc supply current 80 ma i cc2 standby mode current (3) 4 ma notes: 1. ice pins are addr[15..0], iaddr[15..0], idata[15..0], eib and irwb 2. maximum 3 pins total from p0[15..0] and p1[15..0] 3. 2.3 ma typical at 25 c, 5 volts. table 6. 3.3v 0.3v operation (z87l01) symbol parameter test condition min max units v oh output high voltage v dd min, i oh max 1.6 v v ohice output high voltage, ice pins (1)v dd min, i ohice max 1.6 v v ol1 output low voltage v dd min, i ol1 max 0.4 v v ol2 output low voltage, ports(2) v dd min, i ol2 max 1.2 v v olice output low voltage, ice pins (1) v dd min, i olice max 0.4 v i l input leakage v in = 0v, v dd -2 2 m a i cc supply current 55 ma i cc2 standby mode current(2) 1.4 ma notes: 1. ice pins are addr[15..0], iaddr[15..0], idata[15..0], eib and irwb 2. maximum 3 pins total from p0[15..0] and p1[15..0] 3. 1.6 ma typical at 25 c, 3.3 volts.
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 10 p r e l i m i n a r y ds96wrl0800 analog characteristics table 7. 1-bit adc (temperature: -20/+70 c) parameter minimum typical maximum units resolution - 1 - bit power dissipation 0.54 (70 c) 1.0 (40 c) 2.75 (-20 c) mw power dissipation, stop mode 0.06 (70 c) 0.2 (40 c) 1.1 (-20 c) mw sample frequency - 8.192 - mhz sample window(1) 29 31 33 ns bandwidth - 60 - mhz supply range(=av dd ) z87l01 Z87001 3.0 4.5 3.6 5.5 v v acquisition time 2 3 8 ns settling time 8 10 18 ns conversion time 4 6 18 ns aperture delay 2 3 8.5 ns aperture uncertainty(2) - - 0.5 ns input voltage range (p-p) 800 1000 1200 mv reference voltage z87l01 Z87001 1.7 (av dd = 3v) 2.7 (av dd =4.5v) 1.9 (av dd = 3.3v) 3.0 (av dd = 5v) 2.1 (av dd = 3.6v) 3.3 (av dd = 5.5v) v v input resistance 10 18 25 kohm input capacitance - 10 - pf notes: window of time while input signal is applied to sampling capacitor; see next figure. uncertainty in sampling time due to random variations such as thermal noise.
Z87001/z87l01 zilog romless spread spectrum cordless phone controller ds96wrl0800 p r e l i m i n a r y 11 1 figure 6. 1-bit adc de?ition of terms acquisition time settling time conversion time (for + latched output clk (16.384mhz) sampling window aperture delay input signal digital output) sampling table 8. 8-bit adc (temperature -20/+70 c) parameter minimum typical maximum units resolution - 6 - bit integral non-linearity - 0.5 1 lsb differential non-linearity - - 0.5 lsb power dissipation (peak) 35 70 mw sample window 5 - 120 ns bandwidth - - 2 msps supply range (=av dd ) z87l01 Z87001 3.0 4.5 3.3 5.0 3.6 5.5 v v input voltage range 0-av dd v conversion time 0.5 - - m s aperture delay 2 3 8.5 ns aperture uncertainty - - 1 ns input resistance - 25 - kohm input capacitance - 10 - pf notes: 1. 8-bit adc only tested for 6-bit resolution.
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 12 p r e l i m i n a r y ds96wrl0800 table 9. 4-bit dac (temperature: -20/+70 c) parameter minimum typical maximum units resolution - 4 - bit integral non-linearity - 0.25 0.5 lsb differential non-linearity - 0.25 1 lsb settling time (1/2 lsb) - - 22.5 ns zero error at 25 c-12mv conversion time (input change to output change) 14 19 76 ns power dissipation, 25 pf load 1.2 (70 c) 20 (40 c) 24.1 (-20 c) mw power dissipation, 25 pf load, stop mode 0.18 (70 c) 1.0 (40 c) 1.1 (-20 c) mw conversion time (input change to output change) 14.5 19.1 75.8 ns rise time (full swing) 11 15 71 ns output slew rate 8 67 96 v/ m s output voltage range - 0.2 av dd to 0.6av dd -v supply range (=av dd ) z87l01 Z87001 3.0 4.5 3.3 5.0 3.6 5.5 v v output load resistance 330 ohm output load capacitance - 25 - pf
Z87001/z87l01 zilog romless spread spectrum cordless phone controller ds96wrl0800 p r e l i m i n a r y 13 1 input/output pin characteristics all digital pins (all pins except v dd , av dd , gnd, agnd, v ref , rx, tx, rssi and pwlv) have an internal capaci- tance of 5 pf. the rx analog input pin has an input capacitance of 10 pf. the rssi analog input pin has an input capacitance of 10 pf. ac electrical characteristics clocks, reset and rf interface table 10. clocks, reset and rf interface no. symbol parameter min max units 1 tpc mclk input clock period (1) 61 61 ns 2 twc mclk input clock pulse width 20 40 ns 3 trc, tfc mclk input clock rise/fall time 15 ns 4 trcc, tfcc clkout output clock rise/fall time 2 6 ns 5 trco, tfco codclk output clock rise/fall time 2 6 ns 6 twr resetb input low width 18 tpc 7 trrf, tfrf rf output controls rise/fall time (2) 2 6 ns notes: 1. mclk is 16.384 mhz 25 ppm 2. rf controls are paon, txsw, rfeon, syle.
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 14 p r e l i m i n a r y ds96wrl0800 adpcm processor interface the Z87001 is a peripheral device for the adpcm proces- sor. the interface from the Z87001 perspective is com- posed of an input address bus, a bidirectional data bus, strobe and read/write input control signals and a ready/wait output control signal. read cycles refer to data transfers from the Z87001 to the adpcm processor. write cycles refer to data transfers from the adpcm processor to the Z87001. table 11. read cycles signal name function direction vxadd[2..0] address bus adpcm proc. to Z87001 vxdata[7..0] data bus bidirectional vxstrb strobe control signal adpcm proc. to Z87001 vxrwb read/write control signal adpcm proc. to Z87001 vxrdyb ready control signal Z87001 to adpcm proc. table 12. write cycles no. symbol parameter min max units 8 tsas address, read/write setup time before strobe falls 10 ns 9 thsa address, read/write hold time after strobe rises 3 ns 10 tadrs data read access time after strobe falls 30 (1) ns 11 thdrs data read hold time after strobe rises 8.5 40 (2) ns 12 tws strobe pulse width 20 13 tsdws data write setup time before strobe rises 10 ns 14 thdws data write hold time after strobe rises 3 ns 15 tadrry data read valid before ready falls 22 ns 16 tdsry strobe high after ready falls 0 ns notes: 1. requires wait state on adpcm processor read cycles 2. requires no write cycle directly following read cycle on adpcm processor
Z87001/z87l01 zilog romless spread spectrum cordless phone controller ds96wrl0800 p r e l i m i n a r y 15 1 ac timing diagrams figure 7. transceiver output signal tpc (1) tfc(3) trc(3) twc(2) mclk mclk resetb 1 23 418 17 16 tfcc(4) trcc(4) clkout tfco(5) trco(5) codclk twr(6) tfrf(7) trrf(7) pao n txsw rxsw rfeon syle
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 16 p r e l i m i n a r y ds96wrl0800 figure 8. read/write cycle timings vxadd vxrwb vxstrb vxdata vxrdyb vxdata write cycle tsas(8) thsa(9) thdws(14) vxadd vxrwb vxstrb vxdata vxrdyb vxdata read cycle tsas(8) thsa(9) thdrs(11) tadrs(10) tsdws(13) tws(12)
Z87001/z87l01 zilog romless spread spectrum cordless phone controller ds96wrl0800 p r e l i m i n a r y 17 1 figure 9. read/write cycle timing with wait state vxrdyb vxdata write cycle with wait state vxadd vxrwb vxstrb vxdata vxrdyb vxdata read cycle with wait state tsas(8) thsa(9) thdrs(11) tadrry(15) vxadd vxrwb vxstrb vxdata tsas(8) thsa(9) thdws(14) tsdws(13) tws(12) tdsry(16) tdsry(16)
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 18 p r e l i m i n a r y ds96wrl0800 pin functions v dd. digital power supply. gnd. digital ground. av dd . analog power supply. agnd. analog ground. v ref (analog reference) . this signal is the reference volt- age used by the high speed analog comparator to sample the rx input signal. rx (analog input) . this is the rx if receive signal from the rf module, input to the analog comparator and fsk demodulator. it is internally biased to the v ref dc voltage. the if signal from the rf module should be ac coupled to the rx pin. tx (analog output) . this is the if transmit signal to the rf module, output from the fsk modulator and transmit 4-bit d/a converter. rxsw (output; active high or low programmable) . this pin reflects the programming of the demodulator turn-on time. txsw (output; active high or low programmable) . con- trol for the receive switch on the rf module. active during receive periods. paon (output; active high or low programmable) . con- trol for the transmit switch on the rf module. active during transmit periods. rfeon (output; active high or low programmable) . on/off control for the rf module. active (on) during wake periods. inactive (off) during sleep periods on the handset. rssi (analog input) . receive signal strength indicator from rf module, input to the rssi 8-bit adc. pwlv (analog output) . power level control for rf module, output from the transmit power 4-bit dac. syle (output) . rf synthesizer load enable: latches new frequency hopping control word of external rf synthesiz- er. programmable polarity. ant[1..0] (output) . control for optional antenna diversity on the rf module. mclk (input) . master clock input. clkout (output) . clock output for external adpcm pro- cessor. codclk (output) . clock output for external voice codec. /resetb (input, active low). reset signal. vxadd[2..0] (input) . address bus controlled by external adpcm processor. the Z87001 acts as peripheral of the z87010 adpcm processor. vxdata[7..0] (input/output) . read/write data bus con- trolled by external z87010 adpcm processor. vxstrb (input) . data strobe signal for the vxdata bus, controlled by external z87010. vxrwb (input) . read/write control for the vxdata bus, controlled by external z87010. vxrdyb (output, active low) . ready control for the vx- data bus. this signal is driven high (de-asserted) by the Z87001 to insert wait states in the z87010 adpcm proces- sor accesses. test (input, active high) . main test mode control. must be set to gnd. hbsw (input with internal pull-up) . control for hand- set/base configuration. must be driven high or not connect- ed for handset, low for base. p0[15..0] (input/output) . general-purpose i/o port. direc- tion is bit-programmable. pins p0[3..0],when configured in input mode, can also be individually programmed as wake- up pins for the Z87001 (wake-up active low; signal internal- ly debounced and synchronized to the bit clock). p1[15..0] (input/output).general-purpose i/o port. direc- tion is bit-programmable. pins p114 and p115, when con- figured in input mode, also behave as individually maskable interrupt pins for the core processor (positive edge-triggered). p0 0 wakeup0 p0 1 wakeup1 p0 2 wakeup2 p0 3 wakeup3 p1 14 int0 p1 15 int2
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 19 p r e l i m i n a r y ds96wrl0800 functional description the functional partitioning of the Z87001 is shown in fig- ure 2. the chip consists of a receiver, a transmitter, and several additional functional blocks.the receiver consists of the following blocks: n receive 1-bit adc n demodulator, including: if downconverter afc (automatic frequency control) limiter-discriminator matched filter bit synchronizer bit inversion frame synchronizer (unique word detector) snr detector n receive frame timing counter n receive buffer and voice interface the transmitter consists of the following blocks: n transmit buffer and voice interface n transmit frame timing counter (used on base station only) n modulator, including: nco bit inversion n transmit 4-bit dac in addition, there are the following shared blocks. n event trigger block, controlling: transmit/receive switch power on/off switches (modulator, demodulator, rf module) antenna switch control (used on base station only for antenna diversity) n 4-bit dac for setting transmit power level n 8-bit adc for sampling the received signal strength indicator (rssi) n dsp core processor n two 16-bit general-purpose i/o ports n z87010 adpcm processor interface basic operation the transmitter and receiver operate in time-division du- plex (tdd): handset and base station transmit and receive alternately. the tdd duty cycle lasts 4 ms and consists of the following events: n at the beginning of the cycle, the frequency is changed (hopping) n the base station transmits a frame of 144 bits while the handset receives n the handset then transmits a frame of 148 bits while the base receives. figure 1. basic time duplex timing base handset tx rx tx rx tdd switching hop 4ms frame frequency hopping guard time guard time 144 bits 148 bits
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 20 p r e l i m i n a r y ds96wrl0800 receive 1-bit adc the incoming receive signal at the rx analog input pin is sampled by a 1-bit analog-to-digital converter at 8.192 mhz. the receive signal is fsk-modulated (frequency shift keying) with a carrier frequency of 10.7 mhz (intermediate frequency, or if). the instantaneous frequency varies be- tween 10.7 mhz plus or minus 32.58 khz. since the data rate is 93.09 kbps, there are 88 samples per data bit. this oversampled data is further processed by the demodulator to retrieve the baseband information. the 1-bit converter is implemented with a fast comparator, which determines whether the rx signal is larger or small- er than a reference signal (vref). the Z87001 internally generates the dc level of both vref and rx input pins. the received signal at 10.7 mhz should thus be ac cou- pled to the rx pin via a coupling capacitor. to ensure ac- curate operation of the converter, the user should also at- tach to the vref pin a network whose impedance matches the dc impedance seen by the rx pin. demodulator the demodulator includes a two-stage if downconverter that brings the sampled receive signal to baseband. the narrow-band 10.7 mhz receive signal, sampled at 8.192 mhz by the 1-bit adc, provides a 2.508 mhz useful image. the first local oscillator used to downconvert this if signal is obtained from a numerically controlled oscillator (nco) internal to the Z87001, at the nominal frequency of 460 khz. the resulting signal is thus at 2.048 mhz (= 2.508 mhz - 460 khz). a second downconversion by a 2.048 mhz signal brings the receive signal to baseband. the exact frequency of the 460 khz nco is slightly adjust- ed by the automatic frequency control (afc) loop for ex- act downconversion of the end signal to the zero frequen- cy. the afc circuit detects any dc component in the output of the limiter-discriminator (see below) when receiv- ing a known sequence of data (preamble). this dc com- ponent is called the ?requency bias? the bias estimate out of the afc can be read by the dsp processor on every frame and subsequently filtered. the processor then adds or subtract this filtered bias to/from the nco control word to correct the nco frequency output. the main element of the demodulator is its limiter-discrim- inator. the limiter-discriminator detects the frequency vari- ations (ideally up to 32.58 khz) and converts them to ? or ??information bits. first, the data is processed through low-pass filters to eliminate high frequency spurious com- ponents introduced by the 1-bit adc. the resulting signal is then differentiated and fed to a matched filter. in the matched filter, an integrate-and-dump operation is per- formed to extract the digital information from its back- ground noise. the symbol clock is provided by the bit synchronizer. the bit synchronizer circuit detects 0-to-1 and 1-to-0 transitions in the incoming data stream in order to synchronize a dig- ital phase-lock loop (dpll). the pll output is the recov- ered bit clock, used to time the receiver on the base sta- tion, and both receiver and transmitter on the handset. to ensure enough transitions in the voice data stream, a pseudo-random bit inversion operation is performed on the outgoing voice data. the inversion is then reversed on the demodulated data. since the data is packed in frames sent alternately from base and handset every 4 ms (tdd), additional synchroni- zation means are necessary. this is realized in a frame figure 2. demodulator block diagram rx signal 460 khz + bias 1-bit adc nco afc 2.048 mhz filter limiter- discriminator snr bit sync frame sync rx buffer ssb
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 21 p r e l i m i n a r y ds96wrl0800 functional description (continued) synchronizer, based on detection of a ?nique word?fol- lowing the preamble. the receiver also features a signal-to-noise ratio detector, which allows the dsp software to detect noisy channels and eliminate them from the frequency hopping cycle. the snr information is also used by the Z87001 software as a measure the current range between handset and base sta- tion. this information allows the adaptive power control al- gorithm to provide sufficient output power to the rf trans- mitter. receive frame counter the receive frame counter is responsible to keep track of time within the frame. it is initialized by the frame synchro- nizer logic on detection of the unique word. it is then clocked by the recovered bit clock from the bit synchroniz- er. on the base station, the receive frame counter is used as time base for the receiver. on the handset, it is used as time base for both receiver and transmitter. receive rate buffer and voice interface the voice signal is generated at the fixed rate of 32 kips by the z87010 processor, and transmitted/received in bursts of 93.09 kips across the air. data buffers in the transmitter and receiver are thus necessary to absorb the rate differ- ences over time. these buffers are called ?ate buffers? they can store up to 144 data bits and are organized as an array of 36 4-bit nibbles. the receive rate buffer stores the received data from the demodulator. incoming bits are arranged in 4-bit nibbles and transferred to successive locations of the rate buffer. when the last location is reached, transfers resume from the beginning (circular buffer). the system design guaran- tees that no buffer overrun nor enduring can occur. the receive rate buffer can be read by the dsp core pro- cessor of the Z87001 or by the z87010 chip. on the Z87001 side, the buffer can be read as a random-access memory: the processor writes the nibble address in an ad- dress register and reads the 4-bit data from a data register. on the z87010 side, a voice processor interface logic han- dles the addressing to automatically present the succes- sive voice nibbles to the z87010 in the order they were re- ceived. transmit rate buffer and voice interface the transmit rate buffer stores the data to be modulated. the data is sourced from the z87010 or the Z87001 core processor. as for the receive rate buffer, the z87010 sees a unique pipe to write to, while the Z87001 dsp core ac- cesses the rate buffer as random-access memory. the modulator reads from the rate buffer as from a circular buffer. transmit frame timing counter on the handset, transmission does not start until the re- ceiver has synchronized itself to the signal received from the base station. the transmission timing is based on the recovered clock. no additional counter is necessary. on the base station, the situation is different. transmission timing is based on a local clock, while the reception? tim- ing is based on the clock recovered from the incoming re- ceived signal. two counters, respectively clocked by local and recovered clocks, are necessary to track the transmit and receive signals. note that the receive clock on the base station tracks the handset? transmit clock, which is also the handset? re- ceive clock and tracks the transmit clock of the base sta- tion. as a result, receive and transmit clocks of the base station have exactly the same frequency; only their phases differ. modulator the modulator consists of a numerically controlled oscilla- tor (nco) which generates an fsk (frequency shift key- ing) signal at the carrier frequency of 2.508 mhz. the car- rier frequency is shifted plus or minus 32.58 khz for a ? or a ??data bit. to facilitate conformance to fcc regula- tions, the transitions from ??to ??or vice-versa are smoothed in order to decrease the amplitude of the side lobes of the transmit signal. in practice, the jump from one frequency to the next is performed in several smaller steps. the carrier frequency is adjustable by the dsp core pro- cessor in order to provide additional frequency adjustment between base and handset. this is provided in case of a frequency offset too large for possible correction by the afc. the modulator also includes bit inversion logic as dis- cussed in the receiver section.
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 22 p r e l i m i n a r y ds96wrl0800 transmit 4-bit dac the transmit dac clocks one new nco value out of the Z87001 every 8.192 mhz period. only the 10.7 mhz alias frequency component of the transmit signal (2.508 + 8.192 mhz image) is filtered, amplified and upconverted to the 900 mhz ism band by the companion rf module. event trigger block the event trigger block is responsible for scheduling the different events happening at the bit and frame levels. the event trigger block receives input from the frame counters as well as the register interface of the dsp core processor. the event trigger schedules the following events: n start of the 4 ms frame: a synthesizer load enable pulse is issued on the syle pin n power-up of the modulator section and transmission of the frame on handset and base station n use of the bit inversion as function of mode n power-up of the demodulator section and reception of the frame on handset and base station n control of paon and txsw output pins, to be used as tdd control signals for the t/r switch as well as the transmitter and receiver chains on the rf module n control of rfeon pin, to be used as general on/off switch on the rf module n control of the Z87001 sleep mode 4-bit dac for setting transmit power level in order to save battery life, the Z87001 only transmits the amount of rf power needed to reach the remote receiver with a sufficient snr margin. the on-board transmit power 4-bit dac provides 4 different voltage levels to the power amplifier in the rf module for that purpose. this dac is di- rectly controlled by the Z87001 software through an output register. 8-bit adc for sampling the received signal strength indicator (rssi) rssi information is typically generated from the last stage of the rf receiver. the rssi is sampled once per frame by the 8-bit adc and used by the Z87001 software to com- pute the necessary transmit power level voltages. dsp core processor a dsp core processor constitutes the heart of the Z87001. the dsp runs the application software which performs the following functions: n register initialization n implementation of high-level phone features; control of phone user interface (keypad, led, etc.) n control of the z87010 adpcm processor n control of the phone line interface n ring detection by dsp processing n communication protocol between handset and base station supporting voice and signalling channels n control of the rf synthesizer and adaptive frequency hopping algorithm n control of the rf power and adaptive power algorithm n control of the demodulator (bit synchronizer loop filter, afc bias estimate filtering) n control of the modulator (carrier frequency) and adaptive frequency alignment n signalling between base and handset to support above features figure 3. modulator block diagram nco 4-bit dac spectral shaping tx buffer tx signal
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 23 p r e l i m i n a r y ds96wrl0800 functional description (continued) the dsp core is characterized by an efficient hardware ar- chitecture that allows fast arithmetic operations such as multiplication, addition, subtraction and multiply-accumu- late of two 16-bit operands. most instructions are executed in one clock cycle. the dsp core is operated at the internal speed of 8.192 mhz. it has an internal ram memory of 512 16-bit words divided in two banks. six register pointers provide circular buffering capabilities and dual operand fetching. three vectored interrupts are complemented by a six-level stack. one interrupt is used by the transceiver, while the two re- maining vectors are mapped into port p1. in the phone system, one of these interrupts is customarily reserved for the z87010 adpcm processor. the other interrupt can be used for custom purposes. the Z87001 may access up to 64k 16 bit words of external rom including 4 words for interrupt and reset vectors. the rom is mapped at addresses 0000h to 3fffh, as shown in figure 13. two 16-bit general-purpose i/o ports two 16-bit general-purpose i/o ports are directly accessi- ble by the dsp core. these input and output pins are typ- ically used for: n implementation of the phone? user interface (keypad, led, optional display, etc.) n control of phone line interface (on/off hook, ring detect) n control of battery charging and detection of low battery conditions n implementation of additional features for customizing of the phone z87010 interface in addition to providing clock signals to the z87010 proces- sor, the Z87001 interfaces to the z87010 through two dif- ferent paths: n a command/status interface n a data interface the command/status interface consists of two dual-port registers accessible by both Z87001 and z87010 dsp core processors. on the Z87001 side, the registers are mapped into the dsp core processor? register interface. to allow access by the z87010, the internal command/sta- tus registers can also be decoded on the pinto of the Z87001. arbitration logic resolves access contentions. the data interface allows the z87010 processor direct ac- cess to the Z87001? receive and transmit rate buffers. the rate buffers are decoded on the pin to of the Z87001, and dedicated voice processor interface logic handles the ad- dressing within the rate buffers. the physical interface between Z87001 and z87010 con- sists of an 8-bit data bus, a 3-bit address bus and control signals, as summarized in the following: this bus is controlled by the z87010. although in the sys- tem the z87010 is enslaved to the Z87001 master, at the physical level the Z87001 acts as a peripheral of the z87010. the mapping of the command status and data interfaces from the z87010 side is given below. figure 4. rom mapping int. vector 0 int. vector 1 int. vector 2 reset vector 64k 0000h 3fffh 3fffh 3ffeh 3ffdh 3ffch user rom (external) vxdata[7.0] data bus vxadd[2.0] address bus vxstrb data strobe vxrwb read/write control vxrdyb read control interface address (vxadd [2.0]) read /write data (vxdata[7.0]) transmit rate buffer 1w ----3210 receive rate buffer 1r ----3210 command 0 r 76543210 status 0 w 76543210
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 24 p r e l i m i n a r y ds96wrl0800 operation automatic frequency control loop (receiver) and modulator afc loop the afc loop consists of a bias estimator block, which de- termines frequency offsets in the incoming signal, an adder, to add this bias to the 460 khz frequency control word driving the nco, and various interface points to the dsp core processor. in particular, the dsp can read the bias estimate data and substitute its own calculated bias value to the nco. the bias estimator accumulates the discriminator output values (image of instantaneous frequency) that exceed a programmable threshold (bias_threshold). the pro- cessor can freeze the bias calculation any time by reset- ting the bias_enable control bit. the accumulated bias, available in bias_error_data, can be used directly to correct the nco frequency. alter- nately, the estimated bias can be read by the dsp, further processed, and written to the core_bias_data field. the dsp controls which value is used by setting the use_core_bias field. the selected value is added to the 460 khz signal which downconverts the receive if sig- nal. the core_bias_data and bias_error_data are two? complement numbers in units of 125 hz. in addition to correcting the difference in clock frequencies on the receiver using the afc loop, a Z87001-base system can also modify the frequency of the remote transmit if signals. the software has access to this frequency through the mod_freq register fields. figure 5. afc loop and processor control core_bias_data bias_error_data second down- bias estimator downconverter nco and bias use_core_bias dsp core processor rx signal 460 khz + bias convertor, discriminator discriminator output bias_enable bias_threshold ? adder
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 25 p r e l i m i n a r y ds96wrl0800 operation (continued) modulator control the mod_freq fields specify the carrier center frequen- cy (should be programmed to 2.508 mhz) and deviation for the fsk signal (should be programmed to 32.58 khz). in addition, wave shaping is performed on bit transitions, in order to satisfy fcc regulations. up to four different inter- mediate deviation values are programmable for each of the two fsk states. the mod_freq fields are program- mable in units of 62.5 hz. bit synchronizer the bit synchronizer circuit is an implementation of the data-transition-tracking loop (dttl), best described in ?elecommunications systems engineering? by w. lind- sey and m. simon (dover 1973; oh. 9 p. 442). its operation is summarized in the following block diagram. table 1. afc and modulator control fields field register bank ext bias_threshold config1 3 ext0 bias_enable sspstate 3 ext2 bias_error_data bias_error 2 ext2 core_bias_data core_bias 2 ext4 figure 6. bit synchronizer loop and processor control in-phase matched filter mid-phase matched filter transition detection error magnitude signed error dsp core processor discriminator output bsync_gain second_order ?y 1 loop filter clock generator recovered ?y 64 division int_sym_err0 int_sym_err1 ?st order bit clock
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 26 p r e l i m i n a r y ds96wrl0800 the loop filter is controlled by the dsp core processor. the dsp core can implement a first order loop by setting the second_order field to zero. typically, the bsync_gain would then be set to ?ivide-by-1?operation to provide a wide closed loop bandwidth and thus a quick acquisition of the bit clock. when the bit clock is in phase with the input data, the loop bandwidth can be narrowed to maintain tracking of the receive clock with minimum impact from signal noise. to reduce the loop bandwidth, the bsync_gain can be set to ?ivide-by-64?the first order gain, while the integrated tracking error (available to the dsp in fields int_sym_err0 and int_sym_err1) can be used by the dsp software to adjust the second_order term. the bit synchronizer relies on transitions in the received bit stream to operate. the bit inversion logic guarantees enough transitions for all transferred data. at the handset, the bit synchronizer must track both fre- quency and phase of the receive signal? data clock. at the base, only the phase must be tracked. the frequency is in- herently correct since the base is the source of the sys- tem? data clock. frame counters the handset only has one frame counter, which times all receive and transmit events. the base station has distinct transmit and receive frame counters. when used in this document without any explicit reference to either base or handset, the terms ?eceive frame counter?and ?ransmit frame counter?refer to both sides. for the handset, both terms refer to the same unique counter. the frame counters are clocked at the bit rate, or 93.09 khz (2.048 mhz/22). each count lasts one bit = 1000/93.09 = 10.74 m s. each frame lasts 4 ms, which corresponds to (372 + 8/22) bits; the frame counters count from 0 to 371, with the last count lasting a bad longer than the other ones; at the end of count 371, the counters wrap around to 0. the ?op?command pulse is asserted to pin syle during count ??of the frame counter (transmit frame counter on the base station). frame synchronizer, timings and rf interface the frame synchronizer tracks the received frames and re- sets the receive frame counter. the synchronization is per- formed by recognizing certain data patterns present in the receive bit stream: a comparison is done on the fly be- tween the data pattern and the incoming bit stream; when the data match, the frame counter is reset. two possible 16-bit data patterns are pre-programmed in the Z87001. one is named uw (unique word) and is used in acquisition mode for first-time synchronization to an in- coming signal. uw can also be used to track an acquired signal. the second pattern is named sync_d and is used to track the received data frames while voice is being transferred. the transition from tracking uw to tracking sync_d is controlled by the dsp processor through the sync_search_word field. uw synchronization when the Z87001 matches the uw, the receive frame counter is reset to the value of uw_location. this value is programmable by the dsp processor. on the handset, where the receive frame counter is used to derive all tim- ings, uw_location actually defines the guard time be- tween the frequency hop command and the beginning of data reception, which starts at frame_counter = (uw_location - 84) as shown in the next figure. on the base station, data reception starts when the receive frame counter equals (uw_location - 84), but this has less significance since the hop pulse is synchronized with the transmit frame counter and there is no fixed relation- ship between transmit and receive frame counters. on the base station, the uw_location should be set to 301. table 2. bit synchronizer control fields field register bank ext bysnc_gain sspstate 3 ext2 int_sym_err1 bit_sync 1 ext2 int_sym_err0 int_sym-err0 0 ext6 second_order bit_sync 1 ext2
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 27 p r e l i m i n a r y ds96wrl0800 operation (continued) two modes of search are programmable through the sync_search_mode field: ?ull search?and ?indow search? the full search is used by the handset when first acquiring the signal from the base station. in full search, the handset is in receive mode and continuously looks for a match with the uw. when a match is found and the time reference established (uw_location is set), the dsp processor on the handset detects the synchronization (see below), switches to time division duplex mode (tdd) and starts receiving and transmitting alternately. the search mode should also be switched to ?indow search?by the dsp software. the window search mode only searches for a match in a certain time window centered around the expected match time. the window size is programmable by the dsp pro- cessor in the window_size field. if the matching does not occur at the expected time, due to so-called ?it slips? the receive frame counter timing is adjusted. note: al- though the bit synchronizer is meant to keep track of time and prevent bit slips when the phone is operating continu- ously in tdd mode, bit slips are still possible when the handset is in standby mode, and only receives once in a while (see description of sleep mode). sync_d synchronization when the dsp processor switches the Z87001 operation to voice mode, the frame synchronization parameters should be modified by the dsp software to: n sync_search_mode = window search n sync_search_word = sync_d pattern in this mode, the receiver searches for the sync_d pat- tern in windows of the incoming data stream. the window size is determined by the window_size field. the transition to voice mode proceeds in two steps, through an intermediate mode. the mode is set by the dsp processor by programming the multiplex_switch field. the three modes are: n smux: initial mode. this mode allows acquisition, afc operation, uw synchronization and signalling; adpcm processor access disabled; bit inversion disabled. n stmux: intermediate mode. this mode allows sync_d frame synchronization and signalling; adpcm processor access disabled; bit inversion enabled. n tmux: voice mode. this mode allows voice transmission, sync_d frame synchronization and signalling; adpcm processor access enabled; bit inversion enabled. in order to detect synchronizations, the software has ac- cess to the sync_acq_ind status field. this field is set by the Z87001 matching hardware every time a match is detected within the right time window. the software must reset the ?nd?bit by setting the sync_acq_clear field. in addition, the software can track the frame timing by reading the frame counter value, available in the frame_counter field. on the base station, where two frame counters are in use, this field returns the value of the transmit frame counter. every time the frame counter wraps around to 0, a frame start indicator bit is set (frame_start_ind status field). the software must reset this ?nd?bit by setting the frame_start_clear field. if the fs_int_enable bit is set, frame starts also trigger interrupts to the dsp pro- cessor. figure 7. frame counter and uw_location on handset 012 uw_location-84 handset syle timing receive data at rx pin frame_counter
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 28 p r e l i m i n a r y ds96wrl0800 the following table summarizes the fields allowing control of frame synchronization and basic frame timing. rf interface several control fields are available in the Z87001 register set to control the timing and polarity of the rf module in- terface signals. a first field, rfeon_polarity, controls the polarity of the rfeon pin. this pin should be used to control the power of the rf module. it is asserted by the Z87001 when the rf module is in use, and de-asserted in sleep mode. the sleep mode is used by the handset to save battery life when no phone call is in process (see ?leep mode? be- low). the syle pin (synthesizer load enable), which carries a ?oad enable?pulse that tells an external rf synthesizer to generate the next rf channel, is controlled by two fields. the hop_enable field is a global enable signal for the syle signals. the syle_polarity field defines the po- larity of the syle pin. the system designer should ensure that the leading edge of the syle pulse triggers channel hopping. in addition to the syle signal, the interface to the most rf synthesizers includes two more input lines, ?ata?and ?lock? for serial programming of the data values defining the rf channel. in order to allow interfacing to various popular synthesizers, the Z87001 does not have dedicated clock and data lines with fixed timing. instead, two general i/o pins from ports p0 and p1 can be controlled in software by the dsp core to realize any particular interface timing. this flexibility is made possible by the high speed, single- cycle architecture of the dsp core. the transmitter control includes a global enable signal for all transmit functions: tx_enable. the transmission start is controlled by the mod_pwr_on field. on the base sta- tion, the value programmed in mod_pwr_on is refer- enced to the transmit frame counter. two additional fields, rftx_pwr_on and rftx_pwr_off, define the duty cycle of the paon out- put pin. on the base station, these fields are referenced to the transmit frame counter. the rftx_polarity bit de- fines the polarity of the paon pin. this pin can be used to control the transmit section and power amplifier of the ex- ternal rf module. on the receive side, two fields define the internal timing of the receiver. the start of reception is controlled by the demod_pwr_on field. stop of reception (and receiver power down) is controlled by the demod_pwr_off field. on the base station, these fields are referenced to the receive frame counter. the rxsw output pin follows the timing defined by the demod_pwr_on and off fields. two additional fields, rfrx_pwr_on and rfrx_pwr_off, define the duty cycle of the txsw out- put pin. on the base station, these fields are referenced to the transmit (!) frame counter. the rfrx_polarity bit defines the polarity of the txsw and rxsw pins. the txsw pin can be used to control the receive section of the external rf module. the various timing control registers reviewed in this para- graph should be programmed differently for handset and base station. if the same rom code is used on base and handset, the software can determine which station it runs on by reading the hand_base_sel bit, which reflects the state of the hbsw pin. table 3. frame synchronizer control fields field register bank ext sync_search-mode sspstate 3 ext2 sync_search_word sspstate 3 ext2 uw_location rx_control 2 ext1 window_size config1 3 ext0 multiplex_switch sspstate 3 ext2 sync_acq_ind sspstatus 3 ext3 sync_acq_clear sspstate 3 ext2 frame_counter sspstatus 3 ext3 fs_int_enable control 1 ext6 frame_start_ind sspstatus 3 ext3 frame_start_clear sspstate 3 ext2 sync_search-mode sspstate 3 ext2
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 29 p r e l i m i n a r y ds96wrl0800 operation (continued) the following figure and table summarize the rf interface control fields. figure 8. rf interface control demodulator dsp core processor tx_enable modulator mod_pwr_on rftx_pwr_off rftx_pwr_on demod_pwr_off demod_pwr_on syle_polarity hop_enable hand_base_sel rfrx_pwr_off rfrx_pwr_on rfrx_polarity rftx_polarity rfeon_polarity syle rxsw txsw pao n hbsw rfeon sleep mode control tx rx,vref table 4. timing and rf interface control fields field register bank ext rfeon_polarity rx_pwr_ctrl 2 ext6 hop_enable sspstate 3 ext2 syle_polarity config1 3 ext0 tx_enable sspstate 3 ext2 mod_pwr_on mod_pwr_ctrl 2 ext5 rfrx_pwr_on/off rfrx_pwr_ctrl 0 ext7 demod_pwr_on/off demod_pwr_ctrl 2 ext6 rfrx_polarity rfrx_pwr_ctrl 0 ext7 rftx_pwr_on/off rftx_pwr_ctrl 2 ext7 rftx_polarity rftx_pwr_ctrl 2 ext7 hand_base_sel ssp_status 3 ext3
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 30 p r e l i m i n a r y ds96wrl0800 sleep mode to save the phone? battery life on the handset, the Z87001 can be operated in sleep mode while the phone is not in use. the sleep mode is entered by software com- mand. the sleep mode first needs to be enabled by setting the sleep_wake field. then a go_to_sleep com- mand puts the processor to sleep by temporarily stopping its clock. the sleep period can be set to last between 4 ms and 1.02 s by programming the sleep_period field. in sleep mode, the rfeon pin is de-asserted. the processor comes out of sleep mode in one of two ways. either the sleep counter counts down to zero, or one of the enabled pins from port p0 is asserted prior to normal expiration of the counter. four port pins (p0[0..4]) can be individually enabled to provide the wake-up function by setting the appropriate bits in p0_wake_enable. typi- cally, these port pins are connected to the telephone key- pad. when the processor core wakes up, the software needs to know how much time it was actually asleep, in order to re- store synchronization to the base station? hopping se- quence. for that purpose, the current value of the sleep counter is available to the processor in sleep_remaining. a value of zero indicates normal ex- piration of the sleep counter. in order to guarantee a good operation of the wake-up pins, the wake-up signals are hardware-denounced by the Z87001. furthermore, these signals are internally syn- chronized to the bit clock. this ensures that the processor has enough time (one bit time = 10.74 ms) to read a stable value of the remaining sleep time and synchronize correct- ly to the base station? hopping sequence. adpcm processor interface and rate buffers the interface to the adpcm processor (z87010) consists of clock control, command/status interface and data inter- face. the data interface gives the adpcm processor ac- cess to the rate buffers. clock interface the Z87001 generates the z87010 clock at 16.384 or 8.192 mhz, as set in vp_clock. in addition, the clock can be stopped and restarted with the vp_stop_clock field in order to reduce power consumption (note: a soft- ware handshaking between Z87001 and z87010 is neces- sary before stopping and after restarting the clock). in addition to providing the z87010 main clock, the Z87001 generates a codclk signal which will be used by the co- dec and by the z87010 to synchronize its data transfers with the Z87001. on the base station, the codclk is sim- ply obtained by dividing the 16.384 mhz input clock. on the handset, the codclk is synchronized to the base station? codclk signal through the receive bit sync log- ic. this ensures that production and consumption of voice data is happening at identical rates on handset and base, eliminating buffer overrun and underrun situations. command/status interface the Z87001 sends commands to the z87010 through the vp_command write-only field. it reads the z87010 sta- tus in the vp_status read-only field. both fields are lo- cated at the same address in the Z87001 register inter- face. a communication protocol should be established in software to ensure correct reception of all commands. dedicated hardware ensures data integrity when both Z87001 and z87010 simultaneously access the same reg- ister. data interface and rate buffers the digitized voice data is communicated between the Z87001 and z87010 through the rate buffers and adpcm processor data interface. the transmit and receive rate buffers each contain 36 4-bit nibbles. to write to the transmit rate buffer, the Z87001 core pro- cessor must first set the nibble address in the tx_buf_addr register field, then write the nibble data through tx_buf_data. if the tx_auto_increment bit is set, the address is automatically incriminated (modu- lo 51 = the number of nibbles in rate buffer + 15 additional data words accessible through tx_buf_data; for more information, see register description) after each data write. this allows the dsp core to write successive nibbles without resetting the address each time. table 5. sleep mode control fields field register bank ext sleep_eake sspstate 3 ext2 go_to_sleep sspstate 3 ext2 sleep_period config2 3 ext1 sleep_remaining config2 3 ext1 p0_wakeup_enable control 1 ext6 table 6. adpcm processor control fields field register bank ext vp_clock config1 3 ext0 vp_stop_clcocks sspstate 3 ext2 vp_command vp_inout 2 ext0 vp_status vp_inout 2 ext0
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 31 p r e l i m i n a r y ds96wrl0800 operation (continued) the operation of the receive rate buffer is identical. the Z87001 core processor must set the nibble address in rx_buf_addr, then read the nibble from rx_buf_data. if the rx_auto_increment bit is set, the read address is automatically incriminated (modulo 36 = number of nibbles in rate buffer) after each data read. this allows the dsp core to read successive nibbles with- out resetting the address each time. through its register interface, the Z87001 also controls which rate buffer addresses the z87010 adpcm proces- sor can access. the nibble addresses are contained in the tx_buf_vp_addr and rx_buf_vp_addr register fields. after the z87010 writes or reads a nibble to or from transmit or receive rate buffer, the corresponding ?p_addr?is automatically incriminated (modulo 36) to the next accessible address. the locations of accessible addresses are individually controlled by the Z87001 in the three tx_rx_nibble_marker register fields. a marker bit equal to ??enables the z87010 to access the corre- sponding address; a bit equal to ??causes the z87010? read or write access to skip to the next nibble that has a marker bit equal to ?? figure 9. rate buffers access and adpcm processor interface demodulator dsp core processor rx_buf_data tx_buf_data tx_rx_nibble_ vp_command rx_buf_vp_addr tx_buf_vp_addr rx rate buffer address decoder vp_status rx_auto_incr. rx_buf_addr tx_auto_incr. tx_buf_addr modulator tx rate buffer marker adpcm proc. interface data addr ctrl Z87001
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 32 p r e l i m i n a r y ds96wrl0800 additional features power control the Z87001 features several means of measuring and controlling power levels. one input pin (rssi) connects an external ?eceive signal strength indicator?to a half flash 8- bit adc in the Z87001. this adc is sampled once per frame during the receive portion of the tdd cycle. the rssi value can be accessed in software in the rssi_data register field. with external multiplexing, the 8-bit adc can be used for additional purposes. the rssi data is used by the software to implement adap- tive power control. in order to determine whether the rssi information is made of signal or noise, the Z87001 includes logic to measure the signal-to-noise ratio (snr) of the re- ceive signal. this snr value is available at the end of ev- ery frame in the snr_estimate register field. it is also used by the adaptive frequency hopping algorithm to de- termine and avoid the noisy channels. finally, a 4-bit dac (resistive ladder) is provided to control rf power output level. the dac is under software control through register field tx_pwr_dac_data. general-purpose i/o ports the Z87001 includes two general-purpose input/output ports, p0 and p1, of 16 bit each. the direction of each bit is independently programmable by setting the register fields direction0 and direction1. then, the software can access the input and output values by accessing data0 and data1. two pins of port p1 (pins 14 and 15), when configured in input mode, also behave as interrupt pins for the core pro- cessor. the software can enable or disable each interrupt by setting the interrupt_0_enable and interrupt_2_enable fields. the interrupts are posi- tive edge-triggered. four pins of port p0 (pins 0 to 3), when configured in input mode, can also be individually programmed as wake-up pins for the Z87001 (see ?leep mode? above). table 7. data and control access to rate buffers field register bank next rx_auto_increment rate_buf_addr 1 ext0 rx_buf_addr rate_buf_addr 1 ext0 tx_auto_increment rate_buf_addr 1 ext0 tx_buf_addr rate_buf_addr 1 ext0 rx_buf_data rate_buf_data 1 ext0 tx_buf_data rate_buf_addr 1 ext1 tx_buf_data rate_buf_data 1 ext1 rx_buf_vp_addr rate_buf_data 1 ext1 tx_buf_vp_addr rate_buf_data 1 ext1 tx_rx_nibble_marker rate_buf_data 1 ext1 table 8. power control field register bank ext rssi_data rssi 2 ext3 snr_estimate rx_control 2 ext1 tx_pwr_dac_data control 1 ext6 rssi_data rssi 2 ext3 snr_estimate rx_control 2 ext3 pin number interrupt number dsp interrupt vector p1 14 int0 3fffh p1 15 int2 3ffdh table 9. general-purpose i/o ports field register bank ext direction0 gpi00dir 3 ext4 data0 gpi00data 3 ext5 direction1 gpi0idir 3 ext6 data1 gpi0idata 3 ext7 interrupt_0_enable control 1 ext6 interrupt_1_enable control 1 ext6
Z87001/z87l01 zilog romless spread spectrum cordless phone controller ds96wrl0800 p r e l i m i n a r y 33 1 register description the Z87001 dsp core processor has four banks of eight registers mapped in the core processor? ?xternal regis- ter?space, as summarized in the following table. table 10. register summary bank address register read description write description table # bank 3 ext0 config1 clock dividers, use core bias, syle polarity, search window size, bias threshold table 25 ext1 config2 remaining sleep time ant0/1 control, sleep period table 26 ext2 sspstate stop vp clock, absent gain, bias enable, tx enable, sync search control, hop enable, frame start control, multiplex control, sleep mode control table 27 ext3 sspstatus frame counter, handset/base, sync search control, frame start control table 28 ext4 gpio0dir general-purpose i/o port 0 direction control table 29 ext5 gpio0data general-purpose i/o port 0 data table 30 ext6 gpio1dir general-purpose i/o port 1 direction control table 31 ext7 gpio1data general-purpose i/o port 1 data table 32 bank 2 ext0 vp_inout adpcm processor status adpcm processor command table 33 ext1 rx_control snr estimate uw location table 34 ext2 bias_error fcw value table 35 ext3 rssi 8-bit adc data (rssi) table 36 ext4 core_bias core bias data table 37 ext5 mod_pwr_ctrl mod_pwr control table 38 ext6 demod_pwr_ctrl rxsw, rfeon pin control table 39 ext7 rftx_pwr_ctrl paon pin control table 40 bank 1 ext0 rate_buf_addr rate buffer address table 41 ext1 rate_buf_data re rate buffer data tx rate buffer data, control data table 42 ext2 bit_sync bit sync monitoring bit sync control table 43 ext3 reserved table 44 ext4 reserved table 44 ext5 reserved table 44 ext6 control int, wakeup pin control, 4-bit dac data (pwlv) table 45 ext7 reserved table 46 bank 0 ext0 reserved table 47 ext1 reserved table 47 ext2 reserved table 47 ext3 reserved table 47 ext4 reserved table 47 ext5 reserved table 47 ext6 int_sym_err0 bit sync monitoring table 47 ext7 rfrx_pwr_ctrl txsw, rxsw pin control table 49
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 34 p r e l i m i n a r y ds96wrl0800 register description (continued) the bank is selectable in software by writing to the core? status register (see table 24). once a bank is selected, each of the eight external registers (ext0 through ext7) can be accessed by a single-cycle software instruction. bank 3 registers table 11. bank switching bank status register bank function bank 0 xxxx xxxx x00x xxxx b test point access, tdd switching control bank 1 xxxx xxxx x01x xxxx b rate buffer access, miscellaneous bank 2 xxxx xxxx x10x xxxx b adpcm processor interface, rf interface, etc. bank 3 xxxx xxxx x11x xxxx b con?uration, status, general-purpose port data and direction table 12. bank 3 registers con? 1 field bank 3 bit position ext0 r/w data description reserved f--------------- r w returns 0 must be set to 1 vp_clock -e-------------- 0 1 controls clkout output pin (clock for adpcm processor). returns 0 clockout=16.384 mhz clockout = 8.192 use_core_bias --d------------- r w0* 1 controls which bias value is used by the downconverters nco as part of the automatic frequency control loop (afc) returns 0 uses bias_error_data value from afc hardware uses core_bias_data value from dsp core syle_polarity ---c------------ r w0 1 controls the polarity of the syle output pin (hop pulse) returns 0 syle is a positive pulse syle is a negative pulse window_size ----ba98-------- r w 0000 0001 1111 de?es the search window size (in bits) for windowed search mode (for unique word or sync_d words). returns 0 window size=1 window size =3 (1 1) window size = 31 (1 15) bias_threshol d -------76543210 r w xxh bias estimator threshold value returns 0 sets the bias value notes: 1. vp_clock. internally synchronized to avoid glitches. changes to this bit take effect immediately. 2. syle_polarity. changes to this bit take effect immediately. 3. bias_threshold. the bias threshold must be coded as a negative value (opposite of the threshold value) coded in 2? complement. the nominal value for the threshold is -46 (=d3h). internally, this value is sign-extended to 13 bits.
Z87001/z87l01 zilog romless spread spectrum cordless phone controller ds96wrl0800 p r e l i m i n a r y 35 1 table 13. bank 3 register ext1 con? 2 field bank 3 bit position ext1 r/w data description antenna_sw_defeat f--------------- r w0 1 controls optional antenna switching (ant0 and ant1 pins) returns 0 enables antenna switching disables antenna switching antenna_sw_offset -edcba98-------- r w xxh controls antenna switching time advancement returns 0 offset in number of 2.048 mhz clock cycles (<108) sleep_period --------76543210 w 00h 01h ffh programs sleep duration in sleep mode illegal sleep period=1 frame (4 ms) sleep period = 255 frames (1.020s) sleep_remaining --------76543210 r 00h 01h ffh returns value of sleep counter when sleep mode is interrupted by a ?ake signal normal expiration of sleep counter one frame left before normal expiration 255 frames left before normal expiration notes: 1. sleep_period. in sleep mode, the rfeon pin is active. changes to this bit take effect immediately. 2. sleep_remaining. a non-zero value indicates that the Z87001 was awakened by a key press activating one of the wake-up pins on port 0. in this case, the processor should immediately reset the sleep_wake field in sspstate to prevent the pro- cess from going back to sleep when the user key press ceases.
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 36 p r e l i m i n a r y ds96wrl0800 register description (continued) table 14. bank 3 register description sspstate field bank 3 bit position ext2 r/w data description sw_syle f--------------- r/w 0* 1 controls accelerated synthesizer programming after sleep not active active stop_codclk -e-------------- r/w 0* 1 inhibits toggling of codec clock output during sleep codclk is free running codclk is frozen high dbp_stop_clock - -d------------- r/w 0* 1 controls toggling of clkout output pin (clock for adpcm processor). clkout is free running clkout is frozen high bsync_gain ---c------------ r/w 0* 1 selects gain for ?st order loop of the bit synchronizer nominal gain gain divided by 64 bias_enable ----b----------- r/w 0* 1 controls closed-loop afc circuit no new bias estimation is performed (latest estimate used) enables bias_error_data updates tx_enable -----a---------- r/w 0* 1 global enable for all transmit functions transmitter disabled transmitter enabled sync_search_word ------9--------- r/w 0* 1 controls the word searched for in search mode search for uw pattern (unique word) search for sync_d pattern sync_search_mode - ------87------- r/w 00* 01 10 11 controls the search mode (and frame synchronization) no search window search (<= uw_location & window_size) full search (during whole frame) not used hop_enable ---------6------ r/w 0 1 enables transmission of the hop pulse on syle pin hop pulse disabled hop pulse enabled sync_acq_clear ----------5----- r w 1->0 clears the sync_acq_ind ?g. returns last value written a transition from 1 to 0 clears the ?g frame_start_clear -----------4---- r w 1->0 clears the frame_start_ind ?g returns last value written a transition from 1 to 0 clears the ?g sleep_wake ------------3--- r/w 0 1 enable bit for entering sleep mode wake mode only sleep mode can be activated by go_to_sleep command multiplex_switch - ------------21- r/w 00* 01 10 11 controls operation of the transceiver smux (bit inversion and adpcm processor access disabled) stmux (bit inv. enabled; adpcm proc. access disabled) reserved tmux (bit inversion and adpcm processor access enabled)
Z87001/z87l01 zilog romless spread spectrum cordless phone controller ds96wrl0800 p r e l i m i n a r y 37 1 go_to_sleep --------------0 r w 0->1 command bit to place the Z87001 in sleep mode returns last value written a transition from 0 to 1 causes Z87001 sleep mode tx_enable -----a---------- r/w 0* 1 global enable for all transmit functions transmitter disabled transmitter enabled sync_search_word ------9--------- r/w 0* 1 controls the word searched for in search mode search for uw pattern (unique word) search for sync_d pattern sync_search_mode - ------87------- r/w 00* 01 10 11 controls the search mode (and frame synchronization) no search window search (<= uw_location & window_size) full search (during whole frame) not used hop_enable ---------6------ r/w 0 1 enables transmission of the hop pulse on syle pin hop pulse disabled hop pulse enabled sync_acq_clear ----------5----- r w 1->0 clears the sync_acq_ind ?g. returns last value written a transition from 1 to 0 clears the ?g frame_start_clear -----------4---- r w 1->0 clears the frame_start_ind ?g returns last value written a transition from 1 to 0 clears the ?g sleep_wake ------------3--- r/w 0 1 enable bit for entering sleep mode wake mode only sleep mode can be activated by go_to_sleep command multiplex_switch -------------21- r/w 00* 01 10 11 controls operation of the transceiver smux (bit inversion and adpcm processor access disabled) stmux (bit inv. enabled; adpcm proc. access disabled) reserved tmux (bit inversion and adpcm processor access enabled) go_to_sleep ---------------0 r w 0->1 command bit to place the Z87001 in sleep mode returns last value written a transition from 0 to 1 causes Z87001 sleep mode notes: 1. dbp_stop_clock. when this bit is set to 1, the adpcm processor clock (clkout) is stopped within two clock periods. when this bit is set to 0, the adpcm processor clock restarts within two clock periods; in every case, the adpcm processor clock min- imum specifications for high time and low time are respected. 2. bsync_gain. changes to this bit take effect immediately. bias_enable. this bit is a global enable for the automatic frequency control. when the bit is set, the afc hardware updates the current bias_error_data during specific time windows, controlled by the event trigger hardware and suitable for a good operation of the afc. when the bit is reset, the afc operation is suspended. however, the current bias_error_data, result- ing from previous bias estimations, can still be used to bias the downconverter nco. changes to the bias_enable bit take effect at the beginning of the frame following the change. 3. tx_enable. global control for all system transmit functions, including paon pin control (timing set by the rftx_pwr_on/off register fields) and power to the modulator and nco (timing set by mod_pwr_on and the wake/sleep modes). 4. changes to this bit take effect immediately. 5. hop_enable. changes to this bit take effect immediately. 6. sleep_wake. this bit must be set to enable the core to put itself to sleep via the go_to_sleep command. the sleep_wake bit must be reset to prevent the core to fall back to sleep after it is awaken by one of the port 0 wake-up pins when the sleep period has not expired. if the bit is not reset, the core will fall right back to sleep when the wake-up input is de-asserted (note that by design, a wake-up input has a minimum of 10 ms duration, to allow the software enough time to safely reset the sleep_wake bit). 7. sync_aqc_clear. this bit must be set to ??again after every ?lear?operation to allow for the next ?lear? 8. frame_start_clear. this bit must be set to ??again after every ?lear?operation to allow for the next ??lear? table 14. bank 3 register description sspstate field bank 3 bit position ext2 r/w data description
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 38 p r e l i m i n a r y ds96wrl0800 register description (continued) table 15. bank 3 register description sspstatus field bank 3 bit position ext3 r/w data description frame_counter fedcba987------ r w 00h ... 173h ... current frame counter value first value at beginning of frame (0) last value at end of frame (371) illegal values no effect reserved ---------65---- r w returns 0 no effect hand_base_sel -----------4--- r w 0 1 re?cts status of handset/base select pin (hbsw) base (hbsw = 0) handset (hbsw = 1) no effect sync_acq_ind ------------3-- r w 0 1 indicates detection of a sync word (uw or sync_d depending on sync_search_word search mode) no sync word detected sync word detected no effect frame_start_ind ------------2-- r w 0 1 indicates start of a new frame no start of new frame (1 written to frame_start_clr) new frame started no effect reserved -------------10 r w returns 0 no effect notes: frame_counter. read the double-buffered current value of the frame counter. on the handset, a single frame counter is used to clock transmit and receive events. on the base station, the transmit frame counter value is returned table 16. bank 3 register description gpio0dir field bit 3 bit position ext4 r/w data description direction0 fedcba9876543210 r/w ..0. ..1. independent control of port 0 pin direction sets pin in input mode sets pin in output mode
Z87001/z87l01 zilog romless spread spectrum cordless phone controller ds96wrl0800 p r e l i m i n a r y 39 1 table 17. bank 3 register description gpio0data field bank 3 bit position ext5 r/w data description data 0 fedcba9876543210 r w xxxxh xxxxh access to port 0 data reads pin values writes output pin values notes: data0. the read value returns the actual pin values and does not depend on the pin directions (i.e. for output pins, the output value is returned unless a contention occurs). table 18. bank 3 register description gpio1dir field bank 3 bit position ext6 r/w data description direction1 f edcba9876543210 r/w ..0. ..1. independent control of port 1 pin direction pin in input mode pin in output mode table 19. bank 3 register description gpio1data field bank 3 bit position ext7 r/w data description data 1 fedcba9876543210 r w xxxxh xxxxh access to port 1 data reads pin values writes output pin values notes: data1. the read value returns the actual pin values and does not depend on the pin directions (i.e. for output pins, the output value is returned unless a contention occurs)
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 40 p r e l i m i n a r y ds96wrl0800 bank 2 registers . table 20. bank 2 register description vp_inout field bank 2 bit position ext0 r/w data description reserved fedcba98-------- r w returns 0 no effect vp_status --------76543210 r xxh access to adpcm processors command/status mailbox reads status byte from adpcm processor vp_command --------76543210 w xxh access to adpcm processors command/status mailbox writes command byte to adpcm processor table 21. bank 2 register description rx_control field bank 2 bit position ext1 r/w data description snr_estimate fedcba9876543210 r xxxxh access to channel measurement (snr) estimate returns the snr value uw_location -------876543210 w xxxxh location of the unique word initializes the value that the receive frame counter is set to on detection of the unique word notes: snr_estimate. this value is updated every frame. it should be read by the software during the frequency hopping guard time of the next frame. table 22. bank 2 register description bias_error field bank 2 bit position ext2 r/w data description bias_error_data fedcba9876543210 r w xxxxh access to the bias estimate from the afc loop. current bias estimate value no effect notes: bias_error_data. this value is used to bias the downconverter? nco if the use_core_bias register field is reset. it is en- coded as a 2? complement number. the unit is 125 hz
Z87001/z87l01 zilog romless spread spectrum cordless phone controller ds96wrl0800 p r e l i m i n a r y 41 1 table 23. bank 2 register description rssi field bank 2 bit position ext3 r/w data description reserved f edcba98-------- r w returns 0 no effect rssi_data -------76543210 r w xxh access to 8-bit adc (can be used for rssi data) returns latest value on 8-bit dac no effect note: rssi_data. this value is sampled once per frame (4ms) approximately at bit 72 (middle) of the received data. table 24. bank 2 register description core_bias field bank 2 bit position ext4 r/w data description reserved fed------------- r w returns 0 no effect core_bias_data ---cba9876543210 r w xxxxh stores bias value for correction of downconverters nco. returns 0 updates bias value notes: core_bias_data.this value is used if the use_core_bias register field is set. it is encoded as a 2? complement number. the unit is 125 hz. table 25. bank 2 register description mod_pwr_ctrl field bank 2 bit position ext5 r/w data description reserved f--------------- r w returns 0 no effect mod_pwr_on -edcba98-------- r w xxh determines modulator turn-on time referenced to the transmit frame counter returns 0 bits 6-0 of turn-on time (=(x modulo 128) -1) reserved --------76543210 r w returns 0 no effect notes: 1. mod_pwr_on. controls the turn-on time for the internal modulator and nco. only the 7 lsbits of the 9-bit value necessary to encode an event (from frame counter 0 to 371) are programmable. the two msbits have fixed values which depend on whether base station or handset is selected: ?0?on the base and ?1?on the handset. the modulator? turn-off time occurs a fixed time (number of bits) after the turn-on time: 144 bits on the base station, 148 bits on the handset. 2. changes to this value take effect immediately. 3. to disable the modulator continuously, clear tx_enable
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 42 p r e l i m i n a r y ds96wrl0800 register description (continued) . table 26. bank 2 register description demod_pwr_ctrl field bank 2 bit position ext6 r/w data description rfeon_polarity f--------------- r w0 1 controls the polarity of the rfeon output pin returns 0 active high active low demod_pwr_on -edcba98-------- r w xxh determines internal power up of demodulator and turn on time of rxsw pin, referenced to the receive frame counter returns 0 bits 6-0 of turn-on time (=(x modulo 128) -1) reserved --------7------- r w returns 0 no effect demod_pwr_off ---------6543210 r w xxh determine internal power down of demodulator and turn off time of rxsw pin, referenced to the receive frame counter returns 0 bits 6-0 of turn-off time (=(x modulo 128) -1) notes: 1. demod_pwr_on, demod_pwr_off. controls internal receive hardware and the rxsw output pin. the turn-on and off times are given in number of received bit periods and are referenced to the receive frame counter. only the 7 lsbits of the 9-bit value are programmable. the two msbits have fixed values which depend on whether base station or handset is selected. for demod_pwr_on, the two bits are ?1?on the base and ?0?on the handset. for demod_pwr_off, the two bits are ?0?on the base and ?1?on the handset 2. changes to these values take effect immediately. 3. to enable receive power continuously, clear tx_enable and set sync_search_mode to full_search (this is the case in acquisition mode). 4. the polarity of the rxsw output pin is controlled by the rfrx_polarity bit in the rfrx_pwr_ctrl register
Z87001/z87l01 zilog romless spread spectrum cordless phone controller ds96wrl0800 p r e l i m i n a r y 43 1 table 27. bank 2 register description rftx_pwr_ctrl field bank 2 bit position ext7 r/w data description rftx_polarity f--------------- r w0 1 controls the polarity of the paon output pin returns 0 active high active low rftx_pwr_on -edcba98-------- r w xxh determines paon output pin turn-on time referenced to the transmit frame counter returns 0 bits 6-0 of turn-on time (=(x modulo 128) -1) reserved --------7------- r w returns 0 no effect rftx_pwr_off ---------6543210 r w xxh determine paon output pin turn-off time referenced to the transmit frame counter returns 0 bits 6-0 of turn-off time (=(x modulo 128) -1) notes: 1. rftx_pwr_on, rftx_pwr_off. controls the paon output pin, and thereby the external rf module? transmitter. the turn-on and off times are given in number of transmitted bit periods and are referenced to the transmit frame counter. only the 7 lsbits of the 9-bit value are programmable. the two msbits have fixed values which depend on whether base station or handset is selected. for rftx_pwr_on, the two bits are ?0?on the base and ?1?on the handset. for rftx_pwr_off, the two bits are ?1?on the base and ?0?on the handset. 2. changes to these values take effect immediately. 3. to disable the transmitter continuously, clear tx_enable in ssp_state.
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 44 p r e l i m i n a r y ds96wrl0800 bank 1 registers table 28. bank 1 register description rate_buf_addr field bank 1 bit position ext0 r/w data description reserved f-------------- r w returns 0 no effect rx_auto_increment -e------------- r w0 1 controls the auto-increment feature of the rx rate buffer returns 0 disables auto-increment enables auto-increment rx_buf_addr --dcba98-------- r w 00h ... 23h ... access to rx rate buffer address returns 0 address 0 ... address 23h = 35 illegal reserved --------7------- r w returns 0 no effect tx_auto_increment ---------6------ r w0 1 controls the auto-increment feature of the tx rate buffer returns 0 disables auto-increment enables auto-increment tx_buf_addr ----------543210 r w 00h ... 23h 24h 25h 26h 27h 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 30h 31h 32h ... access to tx rate buffer address returns 0 address 0 ... address 23h = 35 tx/rx rate buffer address for adpcm processor accesses tx/rx nibble marker bits [15..0] tx/rx nibble marker bits [31..16] tx/rx nibble marker bits [35..32] mod_freq_dev 0 mod_freq_dev 1 mod_freq_dev 2 mod_freq_dev 3 mod_freq_dev 4 mod_freq_dev 5 mod_freq_dev 6 mod_freq_dev 7 mod_freq_dev 8 mod_freq_dev 9 mod_center_freq illegal
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 45 p r e l i m i n a r y ds96wrl0800 register description (continued) table 29. bank 1 register description rate_buf_data field bank 1 bit position ext1 r/w data description rx_buf_data ------------3210 rxh access to the rx rate buffer data reads value at current rx_buf_addr address (0 to 23h) tx_buf_data ------------3210 w xxxxh access to the tx rate buffer data writes value at current tx_buf_addr address (0 to 23h) tx_buf_vp_addr --dcba98-------- w xxh sets the initialization value of the tx rate buffer address used for adpcm processor accesses writes initialization value (tx_buf_addr address= 24h) rx_buf_vp_addr ----------543210 w xxh sets the initialization value of the rx rate buffer address used for adpcm processor accesses writes initialization value (tx_buf_addr address= 24h) tx_rx_nibble_marker fedcba9876543210 w xxxxh sets the nibble marker register for tx and rx rate buffer accesses by adpcm processor write nibble marker value (tx_buf_addr= 25h to 27h) mod_freq fedcba9876543210 w xxxxh access to modulator settings writes modulator setting value (tx_buf_addr=28h to 32h) note: the meaning and address for any rate_buf_data is set in the rate_buf_addr register. mod_freq. the unit for center frequency and frequency deviation words is 62.5 hz. these words are encoded as 2? complement numbers. the meaning and address for any rate_buf_data is set in the rate_buf_addr register. mod_freq. the unit for center frequency and frequency deviation words is 62.5 hz. these words are encoded as 2? complement numbers. table 30. bank 1 register description bit_sync field bank 1 bit position ext2 r/w data description int_sym_err1 fedcba9876543210 r xxxxh read access to the integrated symbol error from the bit synchronizers second order loop reads error data bits [23..8] (bits [7..0] are in bank 0, ext6) second_order fedcba9876543210 w xxxxh write access to the bit synchronizers second-order loop writes second order loops 16-bit value
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 46 p r e l i m i n a r y ds96wrl0800 table 31. bank 1 register description reserved field bank 1 bit position ext3 ext4 ext5r/w data description reserved fedcba9876543210 r w 0000h returns 0 must be left alone or written to 0000h (or unpredictable results may occur) table 32. bank 1 register description control field bank 1 bit position ext6 r/w data description reserved fedcb----------- r w returns 0 no effect fs_int_enable -----a---------- r/w 0* 1 controls frame start interrupt (int1) disables frame start interrupt enables frame start interrupt interrupt_0_enable ------9--------- r/w 0* 1 controls interrupt 0 (int0 on p114) disables interrupt 0 enables interrupt 0 interrupt_2_enable -------8-------- r/w 0* 1 controls interrupt 2 (int2 on p115) disables interrupt 2 enables interrupt 2 p0_wakeup_enable --------7654---- r/w 0000* 1xxx x1xx xx1x xxx1 controls wake-up pins (p0[3..0]) disables all wake-up pins enables p03 as wake-up pin (if in input mode) enables p02 as wake-up pin (if in input mode) enables p01 as wake-up pin (if in input mode) enables p00 as wake-up pin (if in input mode) tx_pwr_dac_data ------------3210 r/w xh access to tx power 4-bit dac output data sets output value note: p0_wakeup_enable. when enabled, pins p0[3..0] are active low wake-up pins for the Z87001 sleep mode. the input signal is internally debounced and synchronized to the bit clock. it is internally given a minimum duration of one bit to allow the software to exit sleep mode safely. table 33. bank 1 register description reserved field bank 1 bit position ext7 r/w data description reserved fedcba9876543210 r w returns 0 no effect
Z87001/z87l01 zilog romless spread spectrum cordless phone controller ds96wrl0800 p r e l i m i n a r y 47 1 bank 0 registers table 34. bank 0 register description reserved field bank 0 bit position ext0 ext1 ext2 ext3 ext4 ext5 r/w data description reserved fedcba9876543210 r w returns 0 no effect table 35. bank 0 register description int_sym_err0 field bank 0 bit position ext6 r/w data description reserved fedcba98-------- r w returns 0 no effect int_sym_err0 --------76543210 r w xxh read access to the integrated symbol error from the bit synchronizers second order loop reads error data bits [7..0] (bits [23..8] are in bank1, ext2) no effect
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 48 p r e l i m i n a r y ds96wrl0800 table 36. bank 0 register description rfrx_pwr_ctrl field bank 0 bit position ext7 r/w data description rfrx_polarity f--------------- r w0 1 controls the polarity of the txsw (and rxsw) output pins returns 0 txsw active low and rxsw active high txsw active high and rxsw active low rfrx_pwr_on -edcba98-------- r w xxh determines txsw output pin turn-on time referenced to the transmit frame counter returns 0 bits 6-0 of turn-on time (=(x modulo 128) -1) reserved --------7------- r w returns 0 no effect rfrx_pwr_off ---------6543210 r w xxh determine txsw output pin turn-off time referenced to the transmit frame counter returns 0 bits 6-0 of turn-off time (=(x modulo 128) -1) notes: 1. rfrx_polarity. caution: notice the inverse polarity of the txsw pin. 2. rfrx_pwr_on, rfrx_pwr_off. controls the txsw output pin. the turn-on and off times are given in number of trans- mitted bit periods and are referenced to the transmit (!) frame counter. only the 7 lsbits of the 9-bit value are program- mable. the two msbits have fixed values which depend on whether base station or handset is selected. for rfrx_pwr_on, the two bits are ?0?on the base and ?1?on the handset. for rfrx_pwr_off, the two bits are ?1 on the base and ?0?on the handset. 3. changes to these values take effect immediately. 4. to disable transmit power continuously, clear tx_enable.
Z87001/z87l01 zilog romless spread spectrum cordless phone controller ds96wrl0800 p r e l i m i n a r y 49 1 instruction set description refer to zilog? z89c00 user? manual, chapter 5 (in- struction set features) and chapter 6 (assembly lan- guage instruction set), for a complete description of the core processor? instruction set. table 37. instruction set summary instruction description opcode synopsis operands # words # cycles example abs absolute value 1001000 1001000 abs[,] ,a a 1 1 1 1 abs nc,a abs a add addition 1001001 1000001 1000100 1000101 1000011 1000001 1000000 add, a, a, a, a, a, a, a, 1 1 2 1 1 1 1 1 1 2 3 1 1 1 add a,p0:0 add a,d0:0 add a,#%1234 add a,@@p0:0 add a,%f2 add a, @p1:1 add a,x and bitwise and 1011001 1010001 1010100 1010101 1010001 1010001 1010000 and, a, a, a, a, a, a, a, 1 1 2 1 1 1 1 1 1 2 3 1 1 1 and a,p2:0 and a,d0:1 and a,#%1234 and a,@@p1:0 and a, %2c and a,@p1:2+loop and a, ext3 call subroutine call 0010100 0010100 call [,]

, 2 2 2 2 call sub1 call z,sub2 ccf clear carry ?g 1001010 ccf none 1 1 ccf cief clear carry flag 1001010 cief none 1 1 cief copf clear op ?g 1001010 copf none 1 1 copf cp comparison 0111001 0110001 0110101 0110011 0110001 0110000 0110100 cp, a, a, a, a, a, a, a, 1 1 1 1 1 1 2 1 1 3 1 1 1 2 cp a,p0:0 cp a,d3:1 cp a,@@p0:0 cp a,%ff cp a,@p2:1+ cp a,stack cp a,#%ffcf dec decrement 1001000 1001000 dec [,] a, a 1 1 1 1 dec nz,a dec a inc increment 1001000 1001000 inc [,] ,a a 1 1 1 1 inc pl,a inc a jp jump 0100110 0100110 jp [,]

, 2 2 2 2 jp nie,label jp label
Z87001/z87l01 romless spread spectrum cordless phone controller zilog 50 p r e l i m i n a r y ds96wrl0800 ld load destination with source 0000000 0000001 0001001 0000001 0000101 0000011 0000111 0000100 0001100 0001010 0000110 0000010 0001001 0000001 0000100 0100101 0000101 0000001 0000000 ld, a, a, a, a, a, a, ,a , , , , , , , , , , , , 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 2 3 3 1 1 ld a,x ld a,d0:0 ld a,p0:1 ld a,@p1:1 ld a,@d0:0 ld a, 124 ld 124, a ld do:0, ext7 ld p1:1,#%fa ld p1:1,ext1 ld @p1:1,#%1234 ld @p1:1+,x ld y,p0:0 ld sr,d0:0 ld pc,#%1234 ld x,@a ld y,@d0:0 ld a,@p0:0-loop ld x, ext6 mld multiply 1010010 1010010 1011011 1011011 mld, [,] , ,, , ,, 1 1 1 1 1 1 1 1 mld a,@p0:0+loop mld a,@p1:0,off mld @p1:1,@p2:0 mld@p0:1,@p1:0,o n mpya multiply and add 1010010 1010010 1011011 1011011 mpya , [,] , ,, , ,, 1 1 1 1 1 1 1 1 mpya a@p0:0 mpya a,@p1:0,off mpya @p1:1,@p2:0 mpya@p0:1,@p1:0, on mpys multiply and subtract 0010010 0010010 0011011 0011011 mpys, [,] , ,, , ,, 1 1 1 1 1 1 1 1 mpys a,@p0:0 mpys a,@p1:0,off mpys @p1:1,@p2:0 mpys@p0:1,@p1:0, on neg negate 1001000 1001000 neg ,a , a a 1 1 1 1 neg nz,a neg a nop no operation 0000000 nop none 1 1 nop or bitwise or 1101001 1100001 1100100 1100101 1100011 1100001 1100000 or , a, a, a, a, a, a, a, 1 1 2 1 1 1 1 1 1 2 3 1 1 1 or a, p0:1 or a, d0:1 or a,#%202 or a,@@p2:1+ or a, %2c or a, @p1:0-loop or a, ext6 table 37. instruction set summary instruction description opcode synopsis operands # words # cycles example
Z87001/z87l01 zilog romless spread spectrum cordless phone controller ds96wrl0800 p r e l i m i n a r y 51 1 pop pop value from stack 0001010 0000100 0000010 0000000 pop 1 1 1 1 1 1 1 1 pop p0:0 pop d0:1 pop @p0:0 pop a push push value onto stack 0001001 0000001 0000001 0000000 0000100 0100101 0000101 push 1 1 1 1 2 1 1 1 1 1 1 2 3 3 push p0:0 push d0:1 push @p0:0 push bu5 push #12345 push @a push @@p0:0 ret return from subroutine 0000000 ret none 1 2 ret rl rotate left 1001000 1001000 rl ,a ,a a 1 1 1 1 rl nz,a rl a rr rotate right 1001000 1001000 rr ,a ,a a 1 1 1 1 rr c,a rr a scf set c ?g 1001010 scf none 1 1 scf sief set ie ?g 1001010 sief none 1 1 sief sll shift left logical 1001000 1001000 sll [,]a a 1 1 1 1 sll nz,a sll a sopf set op ?g 1001010 sopf none 1 1 sopf sra shift right arithmetic 1001000 1001000 sra,a ,a a 1 1 1 1 sra nz,a sra a sub subtract 0011001 0010011 0010100 0010101 0010011 0010001 0010000 sub, a, a, a, a, a, a, a, 1 1 2 1 1 1 1 1 1 2 3 1 1 1 sub a,p1:1 sub a,d0:1 sub a,#%2c2c sub a,@d0:1 sub a,%15 sub a, @p2:0-loop sub a, stack xor bitwise exclusive or 1111001 1110001 1110100 1110001 1110011 1110001 1110000 xor , a, a, a, a, a, a, a, 1 1 2 1 1 1 1 1 1 2 3 1 1 1 xor a, p2:0 xor a,d0:1 xor a,#13933 xor a,@p2:1+ xor a, %2f xor a, @p2:0 xor a, bus table 37. instruction set summary instruction description opcode synopsis operands # words # cycles example

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